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? semiconductor components industries, llc, 2015 december, 2015 ? rev. 0 1 publication order number: ncp81246/d ncp81246 three-rail controller with svid interface for imvp8 cpu applications the ncp81246 contains a two-phase, and two single-phase buck regulators optimized for intel imvp8 compatible cpus. the two-phase controller combines true differential voltage sensing, differential inductor dcr current sensing, input voltage feed-forward, and adaptive voltage positioning to provide accurately regulated power for imvp8 gt rails. the two single-phase controllers can be used for core, sa and gtus rails. both make use of on semiconductor?s patented enhanced rpm operation. rpm control maximizes transient response while allowing for smooth transitions between discontinuous frequency scaling operation and continuous mode full power operation. the single-phase rails have an ultralow offset current monitor amplifier with programmable offset compensation for ultra high accuracy current monitoring. the ncp81246 offers three internal mosfet drivers with a single external pwm signal. two-phase rail features ? dual edge modulation for fastest initial response to transient loading ? high performance operational error amplifier ? digital soft start ramp ? dynamic reference injection ? (patent #us7057381) ? accurate total summing current amplifier(patent #us6683441) ? dual high impedance differential voltage and total current sense amplifiers ? phase-to-phase dynamic current balancing ? true differential current balancing sense amplifiers for each phase ? adaptive voltage positioning (avp) ? switching frequency range of 300 khz ? 750 khz ? vin range 4.5 v to 25 v ? start-up into pre-charged loads while avoiding false ovp ? ultrasonic operation ? these devices are pb?free, halogen free/bfr free and are rohs compliant single-phase rail features ? enhanced rpm control system ? ultra low offset iout monitor ? dynamic vid feed-forward ? programmable droop gain ? zero droop capable ? thermal monitor ? ultrasonic operation ? adjustable vboot ? digitally controlled operating frequency marking diagram www. onsemi.com 52 1 qfn52 mn suffix case 485be ncp81246 = specific device code f = wafer fab a = assembly site wl = lot id yy = year ww = work week = pb-free package ncp81246 fawlyyww device package shipping ? ordering information NCP81246MNTXG qfn52 (pb?free) 5000 / tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncp81246 www. onsemi.com 2 figure 1. application schematic vcc_core vcc_gt vcc_sa ncp81246 ilim iout comp vsn vsp vrmp vrrdy en comp fb diffout vsn vsp iout tsense psys sclk alert sdio vrhot tsense iout ilim comp vsn vsp vcc +5 v +5 v gnd skt_sns+ skt_sns? v pu v pu v pu pvcc bst hg sw lg csp csn bst hg sw lg csp1 bst hg sw lg csp2 csref cssum ilim cscomp pwm dron csp csn skt_sns+ skt_sns? skt_sns+ skt_sns? v in v in v in v in vrdv hg sw lg vcc en pwm bst ncp81253 v in ntc ntc ntc ntc ntc batt chrgr
ncp81246 www. onsemi.com 3 figure 2. 2-phase rail block diagram ? + ? + ? + vr_hot# psys/tsense_1b sdio alert# sclk vr_rdy rosc iccmax_2ph iccmax_1a iccmax_1b addr_vboot tsense_2ph tsense_1a vramp vcc en pvcc gnd thermal monitor drvon enable svid interface & logic enable vr ready logic adc mux (vsp?vsn) iout_2ph iout_1a iout_1b enable uvlo&en comparators power state gate enable drvon iout pvcc ps# zero current detection config gate drivers ps# ovp ocp comp oscillator & ramp generators ps# vrmp addr_vboot pwm generators pvm1 pvm2 current balance amplifiers iph2 iph1 ps# ocp ovp dac data registers dac feed-forward dac ovp ovp vsp vsn 1.3 v csref ovp max ovp current sense amp error amp 1.3 v cscomp ocp buffer over-current comparators over-current programming current monitor vsp vsn diff amp vsp_2ph vsn_2ph diffout_2ph fb_2ph comp_2ph cscomp_2ph cssum_2ph csref_2ph ilim_2ph iout_2ph drvon csp2_2ph csp1_2ph pwm hg1 sw1 lg1 hg2 sw2 lg2
ncp81246 www. onsemi.com 4 figure 3. single-phase block diagram a v = 1 ? + current sense amp vsn_1x vsp_1x vsn vsp + ? + dac feed-forward dac gm dac feed-forward current from svid interface dac droop current offset adjust ovp ref ocp ref ovp ocp ovp curr ocp drvon comp ramp pwm ps# dac vrmp freq over-current programming over-current comparators current monitor iout pvcc pvcc addr_vboot comp_1x csp_1x csn_1x ilim_1x iout_1x hg3 sw3 lg3 hg2 sw2 lg2 pwm gate driver gate driver config zero current detection ramp generator pwm generator 1-phase a only 1-phase b only
ncp81246 www. onsemi.com 5 figure 4. pin configuration vsn_2ph vsp_2ph psys vsp_1b vsn_1b comp_1b ilim_1b csn_1b csp_1b iout_1b vr_rdy en pwm/addr_vboot 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 bst1 hg1 sw1 lg1/rosc pvcc lg2/iccmax_1a sw2 hg2 bst2 lg3/iccmax_1b sw3 hg3 bst3 dron sclk alert# sdio vr_hot# iout_1a csp_1a csn_1a ilim_1a comp_1a vsn_1a vsp_1a tsense_1a 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 iout_2ph diffout_2ph/iccmax_2ph fb_2ph comp_2ph ilim_2ph cscomp_2ph cssum_2ph csref_2ph csp2_2ph csp1_2ph tsense_2ph vrmp vcc ncp81246 tab: ground (not to scale) table 1. ncp81246 pin descriptions pin no. symbol description 1 iout_2ph a resistor to ground programs iout gain for the two-phase regulator. 2 diffout_2ph/ iccmax_2ph output of the two-phase regulator?s differential remote sense amplifier. during start-up, the two-phase regulator?s iccmax is programmed with a pull-down on this pin. 3 fb_2ph error amplifier voltage feedback for two-phase regulator. 4 comp_2ph output of the error amplifier and the inverting inputs of the pwm comparators for two-phase regulator. 5 ilim_2ph over-current threshold setting ? programmed with a resistor to cscomp_2ph for two-phase regulator. 6 cscomp_2ph output of total-current-sense amplifier for two-phase regulator. 7 cssum_2ph inverting input of total-current-sense amplifier for two-phase regulator. 8 csref_2ph total-current-sense amplifier reference voltage input for two-phase regulator. 9 csp2_2ph non-inverting input to current-balance amplifier for phase 2 of the two-phase regulator. 10 csp1_2ph non-inverting input to current-balance amplifier for phase 1 of the two-phase regulator. 11 tsense_2ph temperature sense input for the two-phase regulator. 12 vrmp feed-forward input of vin for the ramp-slope compensation. the current fed into this pin is used to control the ramp of the pwm slopes. 13 vcc power for the internal control circuits. a decoupling capacitor is connected from this pin to ground. 14 bst1 high-side bootstrap supply for phase 1 of the two-phase regulator. 15 hg1 high-side fet gate driver output for phase 1 of the two-phase regulator.
ncp81246 www. onsemi.com 6 table 1. ncp81246 pin descriptions (continued) pin no. description symbol 16 sw1 current return for high-side fet gate driver for phase 1 of the two-phase regulator. 17 lg1/rosc low-side fet gate driver output for phase 1 of the two-phase regulator. during start-up rosc is programmed with a pull-down resistor on this line. 18 pvcc power supply for all three internal fet gate drivers. 19 lg2/iccmax_1a low-side fet gate driver output for phase 2 of the two-phase regulator, or output of single-phase regulator 1b. during start-up, regulator 1a?s iccmax is programmed with a pull-down on this pin. 20 sw2 current return for high-side fet gate driver for phase 2 of the two-phase regulator, or for single-phase regulator 1b. 21 hg2 high-side fet gate driver output for phase 2 of the two-phase regulator, or for single-phase regulator 1b. 22 bst2 high-side bootstrap supply for phase 2 of the two-phase regulator, or for single-phase regulator 1b. 23 lg3/iccmax_1b low-side fet gate driver output for single-phase regulator 1a. during start-up, regulator 1b s iccmax is programmed with a pull-down on this pin. 24 sw3 current return for high-side fet gate driver for single-phase regulator 1a. 25 hg3 high-side fet gate driver output for single-phase regulator 1a. 26 bst3 high-side bootstrap supply for single-phase regulator 1a. 27 tsense_1a temperature sense input for the single-phase regulators. 28 vsp_1a differential output voltage sense positive for single-phase regulator 1a. 29 vsn_1a differential output voltage sense negative for single-phase regulator 1a. 30 comp_1a compensation for single-phase regulator 1a. 31 ilim_1a a resistor to ground programs the current-limit for single-phase regulator 1a. 32 csn_1a differential current sense negative for single-phase regulator 1a. 33 csp_1a differential current sense positive for single-phase regulator 1a. 34 iout_1a a resistor to ground programs iout gain for single-phase regulator 1a. 35 vr_hot# thermal logic output for over temperature. 36 sdio serial vid data interface 37 alert# serial vid alert# 38 sclk serial vid clock 39 dron bi-directional fet driver enable 40 pwm/ addr_vboot pwm output for phase 2 of the two-phase regulator or single-phase regulator 1b. during start-up, a resistor to ground programs svid address and vboot options for all three rails. 41 en enable. high enables all three rails. 42 vr_rdy vr_rdy indicates all three rails are ready to accept svid commands. 43 iout_1b a resistor to ground programs iout gain for single-phase regulator 1b. 44 csp_1b differential current sense positive for single-phase regulator 1b. 45 csn_1b differential current sense negative for single-phase regulator 1b. 46 ilim_1b a resistor to ground programs the current-limit for single-phase regulator 1b. 47 comp_1b compensation for single-phase regulator 1b. 48 vsn_1b differential output voltage sense negative for single-phase regulator 1b. 49 vsp_1b differential output voltage sense positive for single-phase regulator 1b. 50 psys/tsense_1b system power signal input. resistor to ground for scaling / temperature sense input for the single-phase regulators. 51 vsp_2ph differential output voltage sense positive for the two-phase regulator. 52 vsn?2ph differential output voltage sense negative for the two-phase regulator.
ncp81246 www. onsemi.com 7 table 2. absolute maximum ratings pin symbol v max v min i source i sink comp_2ph vcc + 0.3 v ?0.3 v 2ma 2ma cscomp_2ph vcc + 0.3 v ?0.3 v 2ma 2ma vsn_2ph gnd + 0.3 v gnd ? 0.3 v 1ma 1ma diffout_2ph / iccmax_2ph vcc + 0.3 v ?0.3 v 2ma 2ma vcc 6.5 v ?0.3 v 100 ma 100 ma pvcc 6.5 v ?0.3 v 100 ma 100 ma vrmp 25 v ?0.3 v 100 ma 100 ma sw_x 35 v 40 v 50 ns ?5 v 100 ma 100 ma bst_x 35 v wrt / gnd 40 v 50 ns wrt / gnd 6.5 v wrt / sw ?0.3 v wrt / sw 100 ma 100 ma lg_x / iccmax_x vcc + 0.3 v ?0.3 v ?2 v 200 ns 100 ma 100 ma hg_x bst + 0.3 v ?0.3 v wrt / sw ?2 v 200 ns wrt /sw 100 ma 100 ma all other pins vcc + 0.3 v ?0.3 v 100 ma 100 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. *all signals referenced to gnd unless noted otherwise. table 3. thermal information description symbol value unit thermal characteristic qfn package (note 1) r ja 68 c/w operating junction temperature range (note 2) t j ?40 to +125 c operating ambient temperature range ?40 to +100 c maximum storage temperature range t stg ? 40 to +150 c moisture sensitivity level qfn package msl 1 *the maximum package power dissipation must be observed. 1. jesd 51?5 (1s2p direct-attach method) with 0 lfm 2. jesd 51?7 (1s2p direct-attach method) with 0 lfm table 4. electrical characteristics ? general (unless otherwise stated: ?40 c ncp81246 www. onsemi.com 8 table 4. electrical characteristics ? general (continued) (unless otherwise stated: ?40 c ncp81246 www. onsemi.com 9 table 4. electrical characteristics ? general (continued) (unless otherwise stated: ?40 c ncp81246 www. onsemi.com 10 table 5. electrical characteristics ? 2-phase rail specific (unless otherwise stated: ?40 c ncp81246 www. onsemi.com 11 table 5. electrical characteristics ? 2-phase rail specific (continued) (unless otherwise stated: ?40 c ncp81246 www. onsemi.com 12 table 6. electrical characteristics ? single phase rail specific (continued) (unless otherwise stated: ?40 c ncp81246 www. onsemi.com 13 table 7. state truth table state vr_rdy pin error amp comp pin ovp & uvp dron pin method of reset por 0 < vcc < uvlo n/a n/a n/a resistive pull down disabled en < threshold uvlo > threshold low low disabled low start-up delay & calibration en > threshold uvlo > threshold low low disabled low dron fault en > threshold uvlo > threshold dron < threshold low low disabled resistive pull up driver must release dron to high soft start en > threshold uvlo > threshold dron > high high operational active/no latch high normal operation en > threshold uvlo > threshold dron > high high operational active/latching high n/a over voltage low n/a dac+ovp high over current low operational last dac code low vout = 0 v low: if reg34h: bit 0 = 0; high: if reg34h: bit 0 = 1; clamped at 0.9 v disabled high, pwm outputs in low state
ncp81246 www. onsemi.com 14 figure 6. state diagram controller por vcc < uvlo vcc > uvlo en = 0 en = 1 disable calibrate phase detect drive off 2.5 ms and cal done vccp > uvlo and dron high ocp condition ovp vs > ovp soft start ramp soft start ramp dac = v boot dac = vid normal vr_rdy uvp vs > uvp vs < uvp 0v boot non-0 v boot
ncp81246 www. onsemi.com 15 general configuration the ncp81246 is a three-rail imvp8 controller, with three internal drivers. the ncp81246 is configured with the two-phase, dual-edge controller providing vgt. table 8 shows the available configurations, and the pull-down resistor required on pin 40 (pwm/ addr_vboot) to configure them. table 8. configurations r (k ) 2ph ph1 ph2 1ph a 1ph b addr v boot (v) d rv1 d rv2 pwm t sense addr v boot (v) d rv3 t sense addr v boot (v) d rv2 pwm t sense 10 1 0 x x 2ph 0 0 x 1a 2 1 x n/a (p sys )) 16.2 1 1.2 x x 2ph 0 1.2 x 1a 2 1 x n/a (p sys ) 22.1 1 0 x x 2ph 0 0 x 1a 2 1.05 x n/a (p sys ) 28.7 1 0 x x 2ph 0 0 x 1a 2 0.95 x n/a (p sys ) 35.7 1 0 x x 2ph 0 0 x 1a 2 1 x n/a (p sys ) 43.2 1 1.2 x x 2ph 0 1.2 x 1a 2 1 x n/a (p sys ) 51.1 1 0 x x 2ph 0 0 x 1a 2 1.05 x n/a (p sys ) 61.9 1 0 x x 2ph 0 0 x 1a 2 0.95 x n/a (p sys ) 71.5 1 0 x x 2ph 2 1 x n/a (p sys ) 0 0 x 1a 82.5 1 1.2 x x 2ph 2 1 x n/a (p sys ) 0 1.2 x 1a 95.3 1 0 x x 2ph 2 1.05 x n/a (p sys ) 0 0 x 1a 110 1 0 x x 2ph 2 0.95 x n/a (p sys ) 0 0 x 1a 127 1 0 x x 2ph 3 0 x 1a 0 0 x 1b 143 1 1.2 x x 2ph 3 1.2 x 1a 0 1.2 x 1b 165 1 0 x x 2ph 3 0 x 1a 0 0 x 1b 187 1 0 x x 2ph 3 0 x 1a 0 0 x 1b switching frequency fsw f sw is programmed on start-up with a pull-down on the lg1 pin. table 9. switching frequency resistor core/gt sa 6.81 k 750 khz 750 khz 14 k 600 khz 600 khz 21.5 k 450 khz 600 khz 28.7 k 300 khz 450 khz serial vid interface (svid) for svid interface communication details please contact intel ? , inc.
ncp81246 www. onsemi.com 16 interleaving in order to minimize stress on the input voltage and simplify input filter design, the ncp81246 monitors the phase-angle relationship between the rails used for core and gt. small adjustments are made to keep phases of both rails from turning on at the same time. priority is given to transient response, i.e. if a phase must turn on to respond to a load increase, the phase will not be gated if the other rail has a phase that is turned on. the feature is intended to reduce loading on the input rail during steady-state conditions. if either rail is operating in dcm mode, this feature will be disabled. ultra-sonic mode ultra-sonic mode forces a minimum switching frequency above audible range when a rail is in dcm mode. two-phase rail voltage compensation the remote sense amplifier output is applied to a type iii compensation network formed by the error amplifier and external tuning components. the non-inverting input of the error amplifier is connected to the same reference voltage used to bias the remote sense amplifier output. two-phase rail remote sense amplifier a high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of the regulator. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points. the remote sense amplifier takes the difference of the output voltage with the dac voltage and adds the droop voltage to v diffout v vsp v vsn 1.3 v v dac (eq. 1) v droop v csref this signal then goes through a standard error compensation network and into the inverting input of the error amplifier. the non-inverting input of the error amplifier is connected to the same 1.3 v reference used for the differential sense amplifier output bias. two-phase rail high performance voltage error amplifier a high performance error amplifier is provided for high bandwidth transient performance. a standard type iii compensation circuit is normally used to compensate the system. figure 7. standard type iii compensation circuit ? + c in r in1 r in2 c f c f1 r f v bias comp error amp
ncp81246 www. onsemi.com 17 differential current feedback amplifiers each phase of the two-phase rail has a low offset differential amplifier to sense that phase current for current balance and per phase ocp protection during soft-start. the inputs to the csnx and cspx pins are high impedance inputs. it is recommended that any external filter resistor rcsn does not exceed 10 k to avoid offset issues with leakage current. it is also recommended that the voltage sense element be no less than 0.5 m for accurate current balance. fine tuning of this time constant is generally not required. the individual phase current is summed into the pwm comparator feedback this way current is balanced via a current mode control approach. r csn l phase c csn dcr (eq. 2) figure 8. ccsn rcsn dcr lphase 12 swnx vout cspx csnx two-phase rail total current sense amplifier the ncp81246 uses a patented approach to sum the phase currents into a single temperature compensated total current signal. this signal is then used to generate the output voltage droop, total current limit, and the output current monitoring functions. the total current signal is floating with respect to csref. the current signal is the difference between cscomp and csref. the rref(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground. the amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the inductor series resistance (dcr). rth is placed near an inductor to sense the temperature of the inductor. this allows the filter time constant and gain to be a function of the rth ntc resistor and compensate for the change in the dcr with temperature. figure 9. ? + r ref1 c ref cscomp csn1 csn2 swn1 swn2 csref cssum r ref2 r ph1 r ph2 c cs1 c cs2 r cs2 r cs1 r th 10 10 1 nf 82.5 k 35.7 k 100 k the dc gain equation for the current sensing: v cscomp csref r cs2 r cs1 r th r cs1 r th r ph i out total dcr (eq. 3)
ncp81246 www. onsemi.com 18 set the gain by adjusting the value of the r ph resistors. the dc gain should be set to the output voltage droop. if the voltage from cscomp to csref is less than 100 mv at iccmax then it is recommend increasing the gain of the cscomp amp. this is required to provide a good current signal to offset voltage ratio for the ilimit pin. when no droop is needed, the gain of the amplifier should be set to provide ~100 mv across the current limit programming resistor at full load. the ntc should be placed near the closest inductor. the output voltage droop should be set with the droop filter divider. the pole frequency in the cscomp filter should be set equal to the zero from the output inductor. this allows the circuit to recover the inductor dcr voltage drop current signal. c cs1 and c cs2 are in parallel to allow for fine tuning of the time constant using commonly available values. it is best to fine tune this filter during transient testing. f z dcr @ 25 c 2 l phase (eq. 4) two-phase rail programming the current limit the current limit thresholds are programmed with a resistor between the ilimit and cscomp pins. the ilimit pin mirrors the voltage at the csref pin and mirrors the sink current internally to iout (reduced by the iout current gain) and the current limit comparators. the 100% current limit trips if the ilimit sink current exceeds 10 a for 50 s. the 150% current limit trips with minimal delay if the ilimit sink current exceeds 15 a. set the value of the current limit resistor based on the cscomp-csref voltage as shown below. (eq. 5) r limit r cs2 r cs1 r th r cs1 r th r ph i out total dcr 10 or (eq. 6) r limit v cscomp csref @ ilimit 10 two-phase rail programming dac feed-forward filter the dac feed-forward implementation is realized by having a filter on the vsn pin. programming r vsn sets the gain of the dac feed-forward and c vsn provides the time constant to cancel the time constant of the system per the following equations. c out is the total output capacitance and r out is the output impedance of the system. figure 10. 12 12 vsn c67 510 pf r68 2.1 k vss_sense r vsn c out r out 453.6 10 6 (eq. 7) (eq. 8) c vsn r out c out r vsn two-phase rail programming droop the signals cscomp and csref are differentially summed with the output voltage feedback to add precision voltage droop to the output voltage. figure 11. ? + cscomp csref cssum 5 6 7 droop (eq. 9) droop dcr r cs r ph two-phase rail programming iout the iout pin sources a current in proportion to the ilimit sink current. the voltage on the iout pin is monitored by the internal a/d converter and should be scaled with an external resistor to ground such that a load equal to icc_max generates a 2 v signal on i out . a pull-up resistor from 5 v vcc can be used to offset the i out signal positive if needed. (eq. 10) r iout 2.0 v r limit 10 r cs2 r cs1 r th r cs1 r th r ph i out icc_max dcr
ncp81246 www. onsemi.com 19 programming icc_max a resistor to ground on the imax pin programs these registers at the time the part is enabled. 10 a is sourced from these pins to generate a voltage on the program resistor. the resistor value should be no less than 2 k . design note: since icc_max is multi-functioned with lg, it is crucial that the ls fet is not turned on during icc_max programming. source current and maximum resistor value must not produce a voltage at the fet gate that will turn it on. keeping the voltage less than 400 mv should be safe. iccmax_2ph: (eq. 11) r iccmax2ph iccmax 2ph 32 127 200 k iccmax_1ph: see table 10 below. table 10. iccmax_1ph resistor 00h (ia) resistor other 02h/03h 6.8 k 23 5k 3 11 k 24 7.8 k 4 14.1 k 25 11 k 5 17.2 k 28 14.1 k 6 22.6 k 29 17.2 k 7 26.5 k 30 20.3 k 8 29.5 k 34 23.4 9 32.8 k 35 36 k 36 figure 12. ? + ? + ? + comp fb diffout vsp vsn r osc detect r d detect on ea iccmax_2ph
ncp81246 www. onsemi.com 20 programming tsense temperature sense inputs are provided. a precision current is sourced out the output of the tsense pin to generate a voltage on the temperature sense network. the voltage on the temperature sense input is sampled by the internal a/d converter. a 100 k ntc similar to the vishay ert?j1vs104ja should be used. see the specification table for the thermal sensing voltage thresholds and source current. figure 13. tsense r tnc 100 k r comp1 0.0 r comp2 8.2 k c filter 0.1 f agnd agnd precision oscillator a programmable precision oscillator is provided. the clock oscillator serves as the master clock to the ramp generator circuit. this oscillator is programmed during start-up by a resistor to ground on the lg1/rosc pin. the oscillator generates triangle ramps that are 0.5~2.5 v in amplitude depending on the vrmp pin voltage to provide input voltage feed forward compensation. programming the ramp feed-forward circuit the ramp generator circuit provides the ramp used by the pwm comparators. the ramp generator provides voltage feed-forward control by varying the ramp magnitude with respect to the vrmp pin voltage. the vrmp pin also has a uvlo function. the vrmp uvlo is only active after the controller is enabled. the vrmp pin is high impedance input when the controller is disabled. the pwm ramp is changed according to the following, (eq. 12) v ramppk pk pp 0.1 v vrmp figure 14. v ramp_pp v in comp_il duty two-phase rail pwm comparators the non-inverting input of the comparator for each phase is connected to the summed output of the error amplifier (comp) and each phase current (i l ? dcr ? phase balance gain factor). the inverting input is connected to the oscillator ramp voltage with a 1.3 v offset. the operating input voltage range of the comparators is from 0 v to 3.0 v and the output of the comparator generates the pwm output.
ncp81246 www. onsemi.com 21 during steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. the steady state duty cycle is still calculated by approximately v out /v in . two-phase rail phase detection sequence during start-up, the number of operational phases and their phase relationship is determined by the internal circuitry monitoring the csp outputs. normally, this rail operates as a two-phase vccgt pwm controller. if csp2_2ph is pulled high to vcc, the two-phase rail operates as a single-phase rail. disable single-phase rail if the ncp81246 is to provide fewer than three rails, one or both of the single-phase rails can be disabled by pulling up their respective csp pin. the main rail cannot be disabled. single-phase rails the architecture of the two single-phase rails makes use of a digitally enhanced, high performance, current mode rpm control method that provides excellent transient response while minimizing transient aliasing. the average operating frequency is digitally stabilized to remove frequency drift under all continuous mode operating conditions. at light load the single-phase rails automatically transition into dcm operation to save power. single-phase rail remote sense error amplifier a high performance, high input impedance, true differential transconductance amplifier is provided to accurately sense the regulator output voltage and provide high bandwidth transient performance. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points through filter networks describe in the droop compensation and dac feedforward compensation sections. the remote sense error amplifier outputs a current proportional to the difference between the output voltage and the dac voltage: (eq. 13) i comp gm v dac v vsp v vsn this current is applied to a standard type ii compensation network. single-phase rail voltage compensation the remote sense amplifier outputs a current that is applied to a type ii compensation network formed by external tuning components clf, rz and chf. figure 15. vsn vsp comp r z clf chf vsn vsp + ? + dac gm single-phase rail ? differential current feedback amplifier each single-phase controller has a low offset, differential amplifier to sense output inductor current. an external lowpass filter can be used to superimpose a reconstruction of the ac inductor current onto the dc current signal sensed across the inductor. the lowpass filter time constant should match the inductor l/dcr time constant by setting the filter pole frequency equal to the zero of the output inductor. this makes the filter ac output mimic the product of ac inductor current and dcr, with the same gain as the filter dc output. it is best to perform fine tuning of the filter pole during transient testing. f z dcr @ 25 c 2 l phase (eq. 14) (eq. 15) f p 1 2 r phsp r th r cssp r phsp r th r cssp c cssp forming the lowpass filter with an ntc thermistor (r th ) placed near the output inductor, compensates both the dc gain and the filter time constant for the inductor dcr change with temperature. the values of r phsp and r cssp are set
ncp81246 www. onsemi.com 22 based on the ef fect of temperature on both the thermistor and inductor. the csp and csn pins are high impedance inputs, but it is recommended that the lowpass filter resistance not exceed 10 k in order to avoid of fset due to leakage current. it is also recommended that the voltage sense element (inductor dcr) be no less than 0.5 m for suf ficient current accuracy. recommended values for the external filter components are: r phsp = 7.68 k r cssp = 14.3 k r th = 100 k , beta = 4300 (eq. 16) c cssp l phase r phsp r th r cssp r phsp r th r cssp dcr using 2 parallel capacitors in the lowpass filter allows fine tuning of the pole frequency using commonly available capacitor values. the dc gain equation for the current sense amplifier output is: (eq. 17) v curr r th r cssp r phsp r th r cssp i out dcr figure 16. r cssp csp a v = 1 ? + r th r phsp c cssp csn to inductor current sense amp curr comp ramp pwm pwm generator t the amplifier output signal is combined with the comp and ramp signals at the pwm comparator inputs to produce the ramp pulse modulation (rpm) pwm signal. single-phase rail ? loadline programming (droop) an output loadline is a power supply characteristic wherein the regulated (dc) output voltage decreases by a voltage v droop , proportional to load current. this characteristic can reduce the output capacitance required to maintain output voltage within limits during load transients faster than those to which the regulation loop can respond. in the ncp81246, a loadline is produced by adding a signal proportional to output load current (v droop ) to the output voltage feedback signal ? thereby satisfying the voltage regulator at an output voltage reduced proportional to load current. v droop is developed across a resistance between the vsp pin and the output voltage sense point. figure 17. vsn vsp vsn vsp + ? + gm r cssp csp a v = 1 ? + r th r phsp c cssp csn to inductor current sense amp t c snssp r drpsp r drpsp c drpsp to vcc_sense v droop r drpsp gm r th r cssp r phsp r th r cssp i out dcr (eq. 18)
ncp81246 www. onsemi.com 23 the loadline is programmed by choosing r drpsp such that the ratio of voltage produced across r drpsp to output current is equal to the desired loadline. (eq. 19) r drpsp loadline gm dcr r phsp r th r cssp r th r cssp single-phase rail ? programming the dac feed-forward filter the dac feed-forward implementation for the single-phase rail is the same as for the 2-phase rail. the ncp81246 outputs a pulse of current from the vsn pin upon each increment of the internal dac following a dvid up command. a parallel rc network inserted into the path from vsn to the output voltage return sense point, vss_sense, causes these current pulses to temporarily decrease the voltage between vsp and vsn. this causes the output voltage during dvid to be regulated slightly higher, in order to compensate for the response of the droop function to the inductor current flowing into the charging output capacitors. r ffsp sets the gain of the dac feed-forward and c ffsp provides the time constant to cancel the time constant of the system per the following equations. c out is the total output capacitance of the system. figure 18. vsn vsp vsn vsp + ? + c snssp r ffsp c ffsp to vcc_sense dac feed-forward dac gm dac feed-forward current from svid interface dac (eq. 20) r ffsp loadline c out 1.35 10 9 ( ) c ffsp 200 r ffsp (nf) single-phase rail ? programming the current limit the current limit threshold is programmed with a resistor (r ilimsp ) from the ilim pin to ground. the current limit latches the single-phase rail off immediately if the ilim pin voltage exceeds the ilim threshold. set the value of the current limit resistor based on the equation shown below. a capacitor must be placed in parallel with the programming resistor to avoid false trips due to the effect of the output ripple current. figure 19. r cssp csp a v = 1 ? + r th r phsp c cssp csn to inductor current sense amp t over-current programming over-current comparators ocp ref ocp r ilimsp gm ilim (eq. 21) r ilimsp 1.3 v gm r th r cssp r phsp r th r cssp i out limit dcr
ncp81246 www. onsemi.com 24 single-phase rail ? programming iout the iout pin sources a current in proportion to the ilimit sink current. the voltage on the iout pin is monitored by the internal a/d converter and should be scaled with an external resistor to ground such that a load equal to iccmax generates a 2 v signal on iout. a pull-up resistor from 5 v vcc can be used to offset the iout signal positive if needed. figure 20. r cssp csp a v = 1 ? + r th r phsp c cssp csn to inductor current sense amp t current monitor r ioutsp gm iout iout (eq. 22) r ioutsp 2v gm r th r cssp r phsp r th r cssp iccmax dcr single-phase rail pwm comparators the non-inverting input of each comparator (one for each phase) is connected to the summation of the output of the error amplifier (comp) and each phase current (i l ? dcr ? phase current gain factor). the inverting input is connected to the triangle ramp voltage of that phase. the output of the comparator generates the pwm output. a pwm pulse starts when the error amp signal (comp voltage) rises above the trigger threshold plus gained-up inductor current, and stops when the artificial ramp plus gained-up inductor current crosses the comp voltage. both edges of the pwm signals are modulated. during a transient event, the duty cycle can increase rapidly as the comp voltage increases with respect to the ramps, to provide a highly linear and proportional response to the step load.
ncp81246 www. onsemi.com 25 protection features under voltage lockouts there are several under voltage monitors in the system. hysteresis is incorporated within the comparators. the ncp81246 monitors the 5 v vcc supply as well as the vrmp pin. the gate drivers monitor both the gate driver vcc and the bst voltage. when the voltage on the gate driver is insufficient it will pull dron low and prevents the controller from being enabled. the gate driver will hold dron low for a minimum period of time to allow the controller to hold off it?s start-up sequence. in this case the pwm is set to the mid state to begin soft start. figure 21. gate driver uvlo restart dac if dron is pulled low the controller will hold off its start-up gate driver pulls dron low during driver uvlo and calibration soft start soft start is implemented internally. a digital counter steps the dac up from zero to the target voltage based on the predetermined setvid_slow rate in the spec table. the pwm signal will start out open with a test current to collect data on svid address and v boot . after the configuration data is collected, if the controller is enabled, the internal and external pwms will be set to 2.0 v mid state to indicate that the drivers should be in diode mode. dron will then be asserted. as the dac ramps the pwm outputs will begin to fire. each phase will move out of the mid state when the first pwm pulse is produced. when a controller is disabled the pwm signal will return to the mid state. figure 22. soft start pwm driver disabled internal test current applied mid state until first pwm pulse or dac reaches target pwm returns to mid state when controller is disabled pwmx dron vcc
ncp81246 www. onsemi.com 26 over current latch-off protection each of the ncp81246 rails compares a programmable current-limit set point to the voltage from the output of its current-summing amplifier. the level of current limit is set with the resistor from the ilim pin to cscomp (two-phase) or to ground (single-phase rails). two-phase rail over current the current through the external resistor connected between ilim and cscomp is then compared to the internal current-limit threshold. if the current generated through this resistor into the ilim pin (i lim ) exceeds the internal current-limit threshold, an internal latch-off counter starts, and the controller shuts down if the fault is not removed after 50 s (immediately shut down for 150% of current-limit threshold) after which the outputs will remain disabled until the v cc voltage or en is toggled. the voltage swing of cscomp cannot go below ground. this limits the voltage drop across the dcr through the current balance circuitry. an inherent per-phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. the over-current limit is programmed by a resistor on the ilim pin. the resistor value can be calculated by the following equations. equation related to the ncp81246: (eq. 23) r ilim i lim dcr r cs r ph i cl where i cl =10 a figure 23. cssum ? + cscomp csref ilim r lim r cs r ph r ph under voltage monitor the output voltage is monitored at the output of the differential amplifier for uvlo. if the output falls more than 300 mv below the dac?droop voltage the uvlo comparator will trip sending the vr_rdy signal low. over voltage protection the output voltage is also monitored at the output of the differential amplifier for ovp. during normal operation, if the output voltage exceeds the dac voltage by 400 mv, the vr_rdy flag goes low, and the output voltage will be ramped down to 0 v. at the same time, the high side gate drivers are all turned off and the low side gate drivers are all turned on. the part will stay in this mode until the v cc voltage or en is toggled. figure 24. ovp threshold behavior uvlo rising dron dac 2.0 v v cc ovp threshold dac + ~400 mv
ncp81246 www. onsemi.com 27 figure 25. ovp behavior at start-up dron dac 2.0 v v out ovp threshold pwm figure 26. ovp during normal operation mode dac vsp_vsn ovp threshold pwm ovp triggered latch off during start-up, the ovp threshold is set to 2.0 v. this allows the controller to start up without false triggering the ovp.
ncp81246 www. onsemi.com 28 package dimensions qfn52 6x6, 0.4p case 485be issue b seating note 4 k 0.10 c (a3) a a1 d2 b 1 14 27 52 e2 52x l bottom view detail c top view side view d a b e 0.10 c pin one location 0.10 c 0.08 c c 40 e a 0.07 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.15 0.25 d 6.00 bsc d2 4.60 4.80 e 6.00 bsc 4.80 e2 4.60 e 0.40 bsc l 0.25 0.45 l1 0.00 0.15 note 3 plane dimensions: millimeters 0.25 4.80 0.40 4.80 52x 0.63 52x 6.40 6.40 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* detail b l1 detail a l alternate terminal constructions l 0.30 ref pitch 52x pkg outline l2 0.15 ref l2 detail c 8 places l2 detail a detail d 8 places 0.11 0.4 9 detail d on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp81246/d intel is a registered trademark of intel corporation in the u.s. and/or other countries. literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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